An integrated circuit (“IC”) is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of signal wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction (“PD”) wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers.
One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. Another example of a PD wiring model is the PD diagonal wiring model, which specifies alternating layers of preferred-direction diagonal wiring. The PD diagonal wiring model can allow for shorter wiring distances than the PD Manhattan wiring model and can decrease the total wirelength needed to interconnect the electronic and circuit components of an IC. The PD diagonal wiring model is described in detail in U.S. patent application Ser. No. 10/334,690, now issued as U.S. Pat. No. 6,988,257, filed Dec. 31, 2002, entitled “Method and Apparatus for Routing,” incorporated herein by reference and in U.S. patent application Ser. No. 10/013,819, now issued as U.S. Pat. No. 7,003,754, filed Dec. 7, 2001, entitled “Routing Method and Apparatus That Use Diagonal Routes,” incorporated herein by reference.
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with signal pins, and (2) interconnect lines (i.e., geometric representations of signal wiring) that connect the signal pins of the circuit modules. A signal net is typically defined as a collection of signal pins that need to be connected.
To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. One EDA tool is a signal wire router that defines routes for interconnect lines that connect the signal pins of signal nets. Signal wire routing is generally divided into two phases: global signal routing and detailed signal routing. For each signal net, global signal routing generates a “loose” route for the interconnect lines that are to connect the signal pins of the signal net. The “looseness” of a global signal route depends on the particular global signal router used. After global signal routes have been created, the detailed signal routing creates specific individual routes for each signal net. A signal wire router that consistently explores diagonal routing directions (referred to herein as a diagonal wire router) is described in the aforementioned patent application titled “Method and Apparatus for Routing.”
Each IC also contains a power grid structure that provides power and ground to each electronic and circuit component of an IC. Each electronic or circuit IC component has a power pin and a ground pin that is connected to the power grid structure. A power net is typically defined as a collection of power pins that need to be connected and a ground net is typically defined as a collection of ground pins that need to be connected.
Power grid structure components include stripes, rails, and vias which must be of a certain strength (i.e., size) to meet design specifications (i.e., minimum specifications that the power grid structure must meet in order to be acceptable for use in the IC). Power grid components, however, compete with signal wiring for area on an IC layer since they take up area on the IC layer that signal wiring could otherwise occupy. Also, power grid structure components can cause substantial blockage of signal wiring paths, especially on layers with the PD diagonal wiring model.
FIG. 1 illustrates a top view of a region of an IC layout having a conventional power grid structure 100. The power grid structure 100 includes stripes 105 and 107, rails 110 and 112, and vias 115 and 117. Stripes 105 and 107 are typically positioned vertically (i.e., parallel to the layout's y-coordinate axis) across an upper layer of the IC and provide power and ground to the IC. A stripe that carries power is referred to as a power stripe 105 and a stripe that carries ground is referred to as a ground stripe 107.
Rails 110 and 112 are typically positioned horizontally (i.e., parallel to the layout's x-coordinate axis) across at least one lower layer of the IC. Each rail is connected to a stripe through vias. A rail connected to a power stripe 105 is referred to as a power rail 110 and a rail connected to a ground stripe 107 is referred to as a ground rail 112.
Vias 115 and 117 are positioned perpendicular to the IC's layers (i.e., parallel to the layout's z-coordinate axis) and distribute power or ground from the stripes to the rails. A via that connects a power stripe 105 to a power rail 110 is referred to as a power via 115 and a via that connects a ground stripe 107 and a ground rail 112 is referred to as a ground via 117.
Multiple vias are arranged in a via array which is used to connect a stripe to a rail. For illustrative purposes, FIG. 1 shows a top view of a via array as enclosed by a rectangular bounding box, the via array being comprised of multiple vias. Since the vias of the power grid structure are positioned upright through the IC, they can cause blocking of the signal wiring needed to interconnect the electronic and circuit components of the IC. The amount of wiring blockage varies from layer to layer depending on the PD wiring model of the layer. As shown in FIG. 1, a 45° diagonal direction arrow 130 and a 135° diagonal direction arrow 132 illustrate how diagonal wiring paths are blocked by vias 115 and 117 of the conventional power grid structure 100.
Conventionally, design engineers manually define the power grid structure by methods of trial and error. For example, designer engineers typically estimate stripe width and stripe spacing values (the distance from one stripe to the next) based on prior experience. Also, a power via 115 (or power via array) is typically located at every intersection of a power stripe 105 and power rail 110 and a ground via 117 (or ground via array) is typically located at every intersection of a ground stripe 107 and ground rail 112. Placing a power via (or power via array) at every power stripe and power rail intersection and a ground via (or ground via array) at every ground stripe and ground rail intersection typically places more vias (or via arrays) in the power grid structure than necessary to meet design specifications for the power grid structure. Thus, the vias of the power grid structure take up more area and cause more signal wiring blockage than necessary on an IC layer. As such, there is a need for an automated method and apparatus for reducing the number of vias (or via arrays) in a power grid structure while still meeting the design specifications for the power grid structure.
In addition, multiple vias are typically arranged in a via array that causes significant diagonal wiring blockage near the edges of the via array. FIG. 8 shows a top view of a conventional via array 800. The via array 800 is enclosed by a rectangular bounding box 805 and is comprised of multiple vias 810. Diagonal direction arrows 820 illustrate how diagonal wiring paths are blocked by vias 810 near the edges of the via array 800. Therefore, there is also a need for via arrays having via arrangements that do not cause significant diagonal wiring blockage near the edges of the via array.